(SNUG San Jose 2013 – Best Paper)
Abstract:Fifos using gray-coded pointers are a common technique for passing data between asynchronous clock domains. However, this technique has a hidden assumption that the skew between the bits is minimal relative to the clock periods involved. This assumption can be violated by P&R tools, and common STA techniques will not flag the problem, since they treat asynchronous domain crossings as unconstrained. This paper discusses the problem and proposes some techniques for constraining these paths.
“Herding Cats” by Paul Zimmer
(Cadence CDNLive 2013 Silicon Valley)
Abstract:The task of creating and maintaining correct timing constraints (SDC) has become increasingly complex over the years. Not only is the timing environment (clocks, generated clocks, exceptions, etc) complex, but it has to work at multiple levels of hierarchy and in multiple places in the flow that use diverse tools – synthesis, place and route, and signoff STA.
This can make it difficult to have a single, uniform sdc script. The result is often a mishmash of bits and pieces of scripts cut and pasted together for each particular phase and tool.
This paper will describe the author’s techniques to rein all of this in and keep to a single source for all sdc. .
“There’s a Better Way To Do It!” by Paul Zimmer
(SNUG San Jose 2010 – Best Paper 3rd place)
Abstract: Finite State Machine design is a common task for ASIC designer engineers. Many designers would prefer to design FSMs in a gui-based environment, but for various reasons no commercial tool for this task has really achieved wide-spread acceptance. The authors have written such a
graphical FSM design tool, and offer it to the engineering community for free under the GNU public license. The gui is written in Java for portability, while the back-end code generation is written in Perl to allow for easy modification. The paper will describe the basic operation of the tool and the format of the Verilog it produces, then go on to describe some of the more advanced features and how they affect the Verilog output.
Note: this paper has been replaced by an up-to-date copy of the fizzim tutorial.
(SNUG San Jose 2007 – Best Paper)
Abstract: Primetime allows multiple clocks to propagate in parallel, allowing multiple operating modes to be timed in a single run. The paper will cover examples of when and how to use multiclock propagation as well as some new (2006.06 and 2006.12) features that make multiclock propagation much easier to use.
Updated May 1, 2009.
“Getting DDRs “write” – the 1x Output Circuit Revisited” by Paul Zimmer
(SNUG San Jose 2006 – Best Paper)
Abstract: A typical DDR write circuit using a 1x clock is discussed and timed using both constraint and model-based techniques. Some SDRAM-specific issues are also discussed, as is the “promiscuous clock” issue in PrimeTime.
21 Jan 2007: Synopsys has dropped support for STAMP models beginning with PrimeTime version 2006.12. Here is an addendum on how to substitute QTM models for STAMP:
“Working with PLLs in PrimeTime – avoiding the phase locked oops” by Paul Zimmer
(SNUG San Jose 2005 – Technical Committee Best Paper)
Abstract: PLLs play an important role in modern high-speed designs, especially when configured for clock tree insertion delay cancellation (IDC). Modeling the behavior of such PLLs accurately in PrimeTime can be a challenge. This paper discusses basic modeling techniques for both standard and multiplier IDC PLLs, duty cycle modeling, jitter and skew, and on-chip-variation effects. The classic OCV/PLL excess pessimism problem will be explained and examined, and a couple of workarounds will be discussed, including a novel new technique developed by the author.
“Automated (Sub)chip Synthesis – Using ACS at the subchip level” by Paul Zimmer
(SNUG San Jose 2004 – Best Paper 3rd place)
Abstract: This paper discusses using ACS at the subchip level – i.e. building the chip using multiple parallel runs of ACS. It describes a set of scripts that simplify this process. You can get the scripts here.
I have updated the scripts to handle lsf. See the README for details. At the same time, I streamlined the way the top is handled (it now uses run_acs.pl like everything else). The paper has been updated to reflect these changes, so you might want to grab the latest copy of the paper (above) as well.
“My Favorite DC/PT Tcl Tricks” by Paul Zimmer
(SNUG San Jose 2003)
Abstract: A grab-bag of handy techniques for using DC/PT tcl, including a set of procs that make defining your own procs much, much easier.
“Working with DDR’s in PrimeTime” by Paul Zimmer and Andrew Cheng
(SNUG San Jose 2002 – Technical Committee Best Paper )
Abstract: This paper discusses techniques for dealing with Double Data Rate interfaces in PrimeTime.
“Complex Clocking Situations Using PrimeTime” by Paul Zimmer
(SNUG San Jose 2001 – Best Paper)
Abstract: This paper illustrates techniques for dealing with such things as clock muxes, cascaded clocks, complex clock waveforms and source synchronous outputs. It also provides a handy technique for handling large numbers of clocks. Finally, the “tidbits” section provides a template for extracting arbitrary information from any PrimeTime (or dcshell) report and getting it into a tcl script automatically.
For all things Verilog and SystemVerilog, take a look at Cliff Cummings’ papers at www.sunburst-design.com. He has written terrific papers on sync/async design, clock domain crossings, RTL coding styles, SV assertions, you name it. I took my SystemVerilog training from Cliff, and it was top-notch.